1. Field of the Invention
The present invention relates to a dynamic memory comprising a plurality of memory cells, each consisting of a selecting transistor and a data-storing capacitor.
2. Description of the Related Art
For a semiconductor memory it is most important that data be stably read from, and stably written into, the memory. For a dynamic memory whose memory cells each comprise one selecting transistor and one data-storing capacitor, it is very important to maintain a reference potential constant, which is compared with the potential of a bit line, thereby to detect data. Unless the reference potential is stable, the read-out margin of the memory cannot be sufficient. (Note: the greater the read-out margin, the smaller the change in the bit-line potential, from which data can be detected.)
It will be explained how to generate a reference potential in a 1 MB DRAM. In the case of this memory having a great memory capacity, an extremely large number of memory cells are connected to each bit line, and the parasitic capacitance C.sub.B of the bit line is naturally very great. On the other hand, there is the trend that the capacitance C.sub.S of the data-storing capacitor of each memory cell is inversely proportional to the memory capacity of the entire memory.
The voltage V0 detected from a memory cell storing logic "0" (i.e., the ground potential) and the potential V.sub.BL which the bit line connected to this cell has before the reading of logic "0" have the following relationship: EQU C.sub.B.V.sub.BL =(C.sub.B +C.sub.S).V0 (1)
Therefore, V0 can be given as follows: ##EQU1##
The voltage V1 detected from a memory cell storing logic "1" (i.e., the V.sub.CC potential) and the potential V.sub.BL which the bit line connected to this cell has before the reading of logic "1" have the following relationship: EQU C.sub.B.V.sub.BL +C.sub.S.V.sub.CC =(C.sub.B +C.sub.S).V1 (3)
Therefore, V1 can be given as follows: ##EQU2##
It is desirable that the reference potential be exactly between V0 and V1, i.e., (V0+V1)/2. To generate a reference potential of this value, the circuit shown in FIG. 1 may be used in a DRAM. The DRAM has a pair of bit lines BL and BL. Memory cell MC is coupled to bit line BL. Cell MC comprised of selecting transistor Q and data-storing capacitor C.sub.S. Transistor Q is to be driven by a signal on word line WLj. Two capacitors C.sub.D are connected at one end to bit line BL. Parasitic capacitor C.sub.B is connected to both bit lines BL and BL. One of capacitors C.sub.D connected to bit line BL is coupled at the other end to dummy word line DWL. The other capacitor C.sub.D connected to bit line BL is coupled at the other end to dummy word line DWL. Latch-type sense amplifier SA is connected between bit lines BL and BL.
To read data from memory cell MC, both bit lines BL and BL are precharged to a predetermined DC potential V.sub.BL by a precharging means (not shown). While the bit lines are being precharged, both dummy word lines DWL and DWL are connected to a V.sub.BL potential source and thus are set at potential V.sub.BL. After bit lines BL and BL have been precharged to potential V.sub.BL, both dummy word lines are disconnected from the V.sub.BL potential source. Then, dummy word lines DWL and DWL are connected to the V.sub.CC potential source and the V.sub.SS potential source, respectively. As a result of this, capacitors C.sub.D are first charged and then discharged. Assuming that the potential of bit line BL changes to Vref after capacitors C.sub.D have been charged and discharged, the potential Vref, the capacitance C.sub.B of capacitors C.sub.B, the capacitances C.sub.D, and the potential V.sub.CC have the following relationship: ##EQU3## As can be understood from equation (5), potential Vref is given as: ##EQU4##
If C.sub.D =1/2C.sub.S, equation (6) can be transformed to the following: ##EQU5##
As is evident from equation (7), the potential exactly half the readout potential of memory cell MC can be generated and used as reference potential Vref, whatever potential bit line BL has before data is read out from memory cell MC. After reference potential Vref has been generated, sense amplifier SA detects the data stored in memory cell MC by comparing voltage V1 or V0 with reference voltage Vref.
FIG. 2 is a circuit diagram showing a conventional DRAM having means for a reference potential based on the principle described above. As is illustrated in this figure, the DRAM comprises pairs of bit lines BL1, BL1, . . . BLm, BLm, memory cells MC, word lines WL1, . . . WLn-1 and WLn, a pair of dummy word lines DWL0 and DWL0, and a pair of dummy word lines DWL1 and DWL1. The DRAM further comprises transistors QE1 to QEm, transistors QP10, QP11 to QPm0, PQm1, latch-type sense amplifiers SA1 to SAm, row decoder RD, dummy word line drive circuits 10 and 20, capacitors C.sub.D 01, C.sub.D 21, . . . C.sub.D 0m, and C.sub.D 2m, and capacitors C.sub.D 11, C.sub.D 31, . . . C.sub.D 1m, and C.sub.D 3m.
Each memory cell is comprised of a selecting transistor Q and a data-storing capacitor C.sub.S. Transistors QE1 to QEm are used to short-circuit the bit line pairs in response to an equalizing signal EQL. Transistors QP10, QP11 to QPm1, and PQm1 are used to set the bit line pairs at potential V.sub.BL in response to the equalizing signal EQL. Latch-type sense amplifiers SA1 to SAm are designed to detect data from the bit line pairs in response to a control signal .phi.SA. Row decoder RD is used to drive word lines WL1, . . . WLn-1, and WLn. Circuit 10 is designed to drive dummy word lines DWL0 and DWL0, and circuit 20 to drive dummy word lines DWL1 and DWL1. Capacitors C.sub.D 01, C.sub.D 21, . . . C.sub.D 0m, and C.sub.D 2m are equivalent to one of two capacitors C.sub.D shown in FIG. 1, and each is connected a bit line BL and dummy word line DWL0 for generating a reference potential in bit line BL. Capacitors C.sub.D 11, C.sub.D 31, . . . C.sub.D 1m, and C.sub.D 3m are equivalent to the other capacitor C.sub.D shown in FIG. 1, and each is connected a bit line BL and dummy word line DWL0 for generating a reference potential in bit line BL.
Dummy word line drive circuit 10 comprises transistor 11 for short-circuiting dummy word lines DWL0 and DWL0 in response to equalizing signal EQL, transistors 12 and 13 for connecting lines DWL0 and DWL0 to potential source V.sub.BL in response to signal EQL, P-channel transistor 14 for connecting dummy word line DWL0 to potential source V.sub.CC in response to selection signal DSE0, and transistor 15 for connecting dummy word line DWL0 to potential source V.sub.SS in response to signal DSE0.
As can be understood from FIG. 2, dummy word line drive circuit 20 is identical in structure to dummy word line drive circuit 10. It is different in the function of its elements. More specifically, transistor 11 short-circuits dummy word lines DWL1 and DWL1 in response to signal EQL; transistors 12 and 13 connect lines DWL1 and DWL1 to potential source V.sub.BL in response to signal EQL; P-channel transistor 14 couples dummy word line DWL1 to potential source V.sub.CC in response to selection signal DSE1; and transistor 15 connects dummy word line DWL1 to potential source V.sub.SS in response to signal DSE1.
Selection signals DSE0 and DSE1, which are used in dummy word line drive circuits 10 and 20, respectively, are selectively set at logic "1" level in accordance with a row-address signal (not shown) which is identical to the one supplied to row decoder RD. All transistors used in either dummy word line drive circuit, except for P-channel transistor 14, are of N-channel type.
Assuming that the memory cells connected to bit line BL of each pair have been selected, then bit line BL and BL of the pair are defined as bit lines BL "1" and BL"1", respectively when the selected cells store logic "1", and as bit lines BL "0" and BL"0", respectively, when the memory cells store logic "0".
Equalizing signal EQL falls from the V.sub.CC level to the V.sub.SS (0V) as is shown in FIG. 3. On the other hand, the potential of a word line WLj (j=1 to n) rises from the V.sub.SS level to the 3/2 V.sub.CC level. Along with the rise of the potential of word line WLj, selection signal DSE0 rises from the V.sub.SS level to the V.sub.CC level. Hence, as is shown in FIG. 3, the potential of dummy word line DWL0 rises from the V.sub.BL level to the V.sub.CC level, whereas the potential of dummy word line DWL0 falls from the V.sub.BL level to the V.sub.SS level. As a result of this, a reference potential is generated in bit lines BL1 to BLm, as may be understood from the description of the circuit shown in FIG. 1. At this time, dummy word lines DWL1 and DWL1 of the other pair are in a "floating" state. Here it is assumed that, of the memory cells simultaneously selected by word line WLj, m cells store logic "0" and n cells store logic "1", where m&lt;&lt;n.
After data items have been read from the selected memory cells to bit lines BL1 to BLm, signal .phi.SA enables sense amplifiers SA1 to SAm to detect data from bit lines BL1 to BLm. Hence, sense amplifiers SA1 to SAm start detecting the data. Thereafter, the potentials of bit lines BL"1" and bit lines BL"0" rise to the V.sub.CC level, whereas the potentials of bit lines BL"0" and bit lines BL"1" fall to the V.sub.SS level. Since dummy word lines DWL1 and DWL1 are in the floating state, their potentials change in the same way as the potential of each bit line BL"1" and the potential of each bit line BL"0", respectively.
The electric charge Q0 accumulated in dummy word line DWL1 or DWL1 before sense amplifiers SA1 to SAm start detecting data is given as follows: EQU Q0=C.sub.DWL.V.sub.BL ( 8)
where C.sub.DWL is the parasitic capacitance of the pair of dummy word lines DWL1 and DWL1.
Assuming that upon lapse of .DELTA.t seconds after the sense amplifiers have started detecting data, the potentials of bit lines BL"0" and BL"1" change to V.sub.BL +V.sub.L and V.sub.BL +V.sub.H, respectively, then the electric charge Q.DELTA.t is accumulated in dummy word line DWL1 or DWL1. This electric charge Q.DELTA.t is presented as follows: ##EQU6##
Since m&lt;&lt;n, the third term of equation (9) has a value far smaller than that of the second term and is negligible. Further, the electric charge accumulated in dummy word line DWL1 or DWL1 either before or after the start of the data reading is retained. Therefore: ##EQU7## From equation (10), we obtained: ##EQU8##
If n=500, C.sub.D =20pF, C.sub.DWL =3pF, V.sub.H =0.3 V, then V.sub.DWL is 230 mV. Hence, the potential of each bit line BL"0", through which logic "0" is read form the memory cells storing logic "0", rises and stays at a high level for some time, as is illustrated in FIG. 3. Immediately after the start of the data reading, the potential difference between the bit lines of any pair is small, and the data detected and latched by the sense amplifier connected to these bit lines is likely to be inverted by noise. A rise of the potential of bit line BL"0" reduces the potential difference between bit lines BL"0" and BL"0", inevitably increasing the possibility that the data detected and latched by the sense amplifier is inverted. In the worst case, the potential of bit line BL"0" rises above that of bit line BL"0" immediately after the start of the data reading, whereby the sense amplifier makes an error, thus reducing the reliability of the data-reading.
The data detected and latched by the sense amplifier may be inverted when m&gt;&gt;n, that is, when more memory cells store logic "0" than those storing logic "1", as will be understood from FIG. 4 which shows how the potentials of the various lines change with time when m&gt;&gt;n. Since dummy word lines DWL1 and DWL1 are in the floating state when logic "1" are read from n memory cells through bit lines BL"1" and BL"1", the potentials of lines DWL1 and DWL1 in the same way as those of bit lines BL"1" and BL"1", respectively. Also in this case, the potential difference between the bit lines of any pair is small immediately after the start of the data reading. In the worst case, the potential of bit line BL"1" falls below that of bit line BL"1" immediately after the start of the data reading, whereby the sense amplifier make an error, thus reducing the reliability of the data-reading.